###############################################################################
##
##  e m 8 6 0 0  -  Motor Controller With Quadrature Inputs
##
##  Revision A
##
##  Designed and manufactured in Australia.
##  Copyright (c) 2009, Embedded Ltd.
##
##  Embedded Ltd makes every effort to ensure the supplied information is
##  correct.  This reference design is provided "as is" without warranty or
##  liability.  It is the user's responsibility to ensure that all code is
##  correct.  Please advise us if you believe our reference code contains an
##  error or omission (support@embedded.com.au).  We value your feedback and
##  strive for continual improvement.
##
###############################################################################

# Spartan 3A-200 (XC3S200A-4VQ100)

CONFIG VCCAUX = 3.3;  # Use 3V3 for VCCAUX

NET "clk50" TNM_NET = "clk50";
TIMESPEC "TS_clk50" = PERIOD "clk50" 20.0 ns HIGH 50%;

# Clock input and global reset output
NET "CLK_50MHZ" LOC = P40 | IOSTANDARD = "LVCMOS33";  # Onboard 50MHz VCXO
NET "RESET_SIG" LOC = P73 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 2;  # Global reset trigger output

# SPI interface to platform flash and system monitor ADC (common SPI bus with separate chip selects)
NET "SYS_SDI"        LOC = P46 | IOSTANDARD = "LVCMOS33" | PULLUP;
NET "SYS_SDO"        LOC = P51 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;
NET "SYS_SCK"        LOC = P53 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;
NET "SYS_FLASH_SS_N" LOC = P27 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;  # Platform flash chip select
NET "SYS_ADC_SS_N"   LOC = P50 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;  # System monitor ADC chip select

# User controlled LEDs
NET "LEDS<0>" LOC = P48 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;  # Closest to QUADRATURE_IN connector
NET "LEDS<1>" LOC = P49 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "LEDS<2>" LOC = P61 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "LEDS<3>" LOC = P62 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "LEDS<4>" LOC = P64 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "LEDS<5>" LOC = P65 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "LEDS<6>" LOC = P70 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;
NET "LEDS<7>" LOC = P71 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;  # Furthest from QUADRATURE_IN connector

# Backplane comms to the slice above (BACKPLANE_UP connector)
NET "COMMS_OUT_P<0>" LOC = P83 | IOSTANDARD = "LVDS_33";  # Use COMS_OUT_[P|N]<0> for clock signal output
NET "COMMS_OUT_P<1>" LOC = P77 | IOSTANDARD = "LVDS_33";  # Tx0
NET "COMMS_OUT_P<2>" LOC = P85 | IOSTANDARD = "LVDS_33";  # Tx1
NET "COMMS_OUT_P<3>" LOC = P88 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;  # Rx0
NET "COMMS_OUT_P<4>" LOC = P93 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;  # Rx1
NET "COMMS_OUT_N<0>" LOC = P84 | IOSTANDARD = "LVDS_33";
NET "COMMS_OUT_N<1>" LOC = P78 | IOSTANDARD = "LVDS_33";
NET "COMMS_OUT_N<2>" LOC = P86 | IOSTANDARD = "LVDS_33";
NET "COMMS_OUT_N<3>" LOC = P89 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;
NET "COMMS_OUT_N<4>" LOC = P94 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;

# Backplane comms to the slice below (BACKPLANE_DOWN connector)
NET "COMMS_IN_P<0>"  LOC = P43 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;  # Use COMS_IN_[P|N]<0> for clock signal input
NET "COMMS_IN_P<1>"  LOC = P34 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;  # Rx0
NET "COMMS_IN_P<2>"  LOC = P30 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;  # Rx1
NET "COMMS_IN_P<3>"  LOC = P32 | IOSTANDARD = "LVDS_33";  # Tx0
NET "COMMS_IN_P<4>"  LOC = P28 | IOSTANDARD = "LVDS_33";  # Tx1
NET "COMMS_IN_N<0>"  LOC = P44 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;
NET "COMMS_IN_N<1>"  LOC = P35 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;
NET "COMMS_IN_N<2>"  LOC = P31 | IOSTANDARD = "LVDS_33" | DIFF_TERM = TRUE;
NET "COMMS_IN_N<3>"  LOC = P33 | IOSTANDARD = "LVDS_33";
NET "COMMS_IN_N<4>"  LOC = P29 | IOSTANDARD = "LVDS_33";

# H-bridge monitoring ADC SPI interface (electrically isolated SPI bus)
NET "HBR_ADC_SDI"  LOC = P6 | IOSTANDARD = "LVCMOS33" | PULLUP;
NET "HBR_ADC_SDO"  LOC = P4 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;
NET "HBR_ADC_SCK"  LOC = P9 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;
NET "HBR_ADC_SS_N" LOC = P5 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;

# H-bridge control interface  (electrically isolated control signals)
NET "HBR_PWM"         LOC = P13 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;  # H-bridge PWM output
NET "HBR_DIR"         LOC = P16 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;  # H-bridge direction output
NET "HBR_BRAKE"       LOC = P15 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 4;  # H-bridge brake output
NET "HBR_FLAG"        LOC = P12 | IOSTANDARD = "LVCMOS33";                            # H-bridge thermal overload flag input

# H-bridge status LEDs (non-isolated)
NET "HBR_LEDS_ACTIVE" LOC = P19 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;  # H-bridge "active" LED output
NET "HBR_LEDS_ALARM"  LOC = P20 | IOSTANDARD = "LVCMOS33" | SLEW = SLOW | DRIVE = 8;  # H-bridge "alarm" LED output

# Quadrature signal inputs (electrically isolated inputs)
NET "HBR_QUAD_I"     LOC = P56 | IOSTANDARD = "LVCMOS33";  # I signal input
NET "HBR_QUAD_Q"     LOC = P59 | IOSTANDARD = "LVCMOS33";  # Q signal input
NET "HBR_QUAD_SYNC"  LOC = P57 | IOSTANDARD = "LVCMOS33";  # SYNC pulse input
NET "HBR_QUAD_LIMIT" LOC = P60 | IOSTANDARD = "LVCMOS33";  # Active-low LIMIT signal input (triggered by any LIMIT input)